Bist structure using multi-input shift register with initial value

Parallel signature analysers are very useful for compression of test response data for VLSI. In the letter the compression result is obtained from a signature of zeros alone or ones alone from a nonzero initial state, rather than from the traditional method of obtaining a nonzero signature from a zeroed MISR register. An algebraic description of such a signature analysis is given, realised by means of the external exclusive-OR-type MISR.