A System on a Chip Architecture of an H.264/AVC Coprocessor for DVB-H and DMB Applications

The new DVB-H standard allows broadcasting of audio/video content to mobile terminals. Such devices underlie severe restrictions concerning processing load and power consumption. The most computational intensive and therewith most power consuming part of such terminals is the decoding of the H.264/AVC video datastream. We present optimization strategies for software-based H.264/AVC video decoding as well as the architecture of an H.264/AVC decoding companion chip with specialized coprocessors, which targets the above mentioned restrictions.