Indium phosphide MISiFET processing using wet chemical surface pre-treatments and evaporated thin silicon interlayers

The use of thin silicon films with wet chemical surface pretreatment for indium phosphide-insulator interface stabilisation of MISiFETs ( MISFETs with a silicon interlayer ) is investigated. InP MISiFETs prepared with the silicon interlayers deposited after H₃ PO₄ surface pre-treatment show a decrease in hysteresis flat band voltage shift. and interface state density. Samples similarly prepared but using an HF surface pre-treatment show a higher threshold voltage shift attributable to high fixed and interface charge density. These effects are consistent with existing models describing the interaction of the silicon with the native oxide of indium phosphide