Title :
VLSI layout generation of a programmable CRC chip
Author :
Sait, Sadiq M. ; Tanvir, Mohammed Shahid K
Author_Institution :
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
fDate :
11/1/1993 12:00:00 AM
Abstract :
VLSI layout generation of a programmable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. The second stage of the compilation process generates a net list of logic gates. The net list so produced is translated to RNL compatible net list by a translator program. The layout subsystem of VPNR is used to generate the VLSI layout of the programmable CRC chip from RNL netlist. The design rules and technology files of MOSIS are used. The layout is viewed in the MAGIC layout editor and simulated by irsim at the transistor-level. The CRC chip can be used in a number of applications. These include areas such as data communications for error detection and correction, digital system testing for test pattern generation and signature analysis, and mass storage devices for parallel information transfers
Keywords :
VLSI; circuit layout CAD; error correction; error detection; logic CAD; logic arrays; specification languages; CRC generator; MAGIC layout editor; MOSIS; VLSI layout generation; VPNR; data communications; design rules; digital system testing; error correction; error detection; functional level simulator; hardware compiler; hardware description language; irsim; layout subsystem; logic gates; logic synthesis; net list; programmable CRC chip; technology files; translator program; Computer errors; Cyclic redundancy check; Data communication; Digital systems; Error correction; Hardware design languages; Logic gates; System testing; Test pattern generators; Very large scale integration;
Journal_Title :
Consumer Electronics, IEEE Transactions on
