Abstract :
As semiconductor technology advances, testing integrated circuits (ICs) has become a challenging task. Semiconductor manufacturers use various methods, including the functional test, the structural test and the speed or delay test. One of the most popular test methods is the leakage current, or IDDQ, test. The article describes the advantages of IDDQ tests. As transistor geometries are scaled further, IDDQ values and variations are projected to increase. Thus, we need to understand the components of the variation in IDDQ to develop the most suitable screening method. IDDQ tests will continue to remain an important and integral component of a test suite. However, IDDQ measurements will need to be supported by rigorous statistical data analysis to reduce yield loss in the future. Manufacturers must he able to define their own statistical procedures to tune pass/fail criteria optimally. It may not be possible to bin the chips until the data from a lot of wafers are collected. The trends in lot-to-lot or wafer-to-wafer variations in IDDQ must be monitored and used in the analysis procedures.
Keywords :
CMOS integrated circuits; data analysis; integrated circuit testing; leakage currents; statistical analysis; CMOS IC testing; integrated circuit testing; leakage current test; pass/fail criteria; semiconductor technology; statistical analysis; statistical data analysis; yield loss; CMOS technology; Circuit testing; Delay; Geometry; Integrated circuit technology; Integrated circuit testing; Leakage current; Loss measurement; Semiconductor device manufacture; Semiconductor device testing;
