DocumentCode
1033864
Title
Rail-to-rail low-power high-slew-rate CMOS analogue buffer
Author
Carrillo, J.M. ; Carvajal, R.G. ; Torralba, A. ; Duque-Carrillo, J.F.
Author_Institution
Dept. of Electron. & Electr. Eng., Univ. of Extremadura, Badajoz, Spain
Volume
40
Issue
14
fYear
2004
fDate
7/8/2004 12:00:00 AM
Firstpage
843
Lastpage
844
Abstract
A low-power rail-to-rail CMOS analogue buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting in suitability for applications with large capacitive loads. Simulated results are provided.
Keywords
CMOS analogue integrated circuits; buffer circuits; differential amplifiers; driver circuits; integrated circuit modelling; power consumption; CMOS simulation; complementary class AB differential paired input; driving circuits; large capacitive loads applications; low-power rail-to-rail high slew rate CMOS analogue buffer; power consumption;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20045047
Filename
1315477
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