Optimal life testing schedule for multiple types of integrated circuits

Life testing of highly reliable integrated circuits (ICs) is a time-consuming process because it usually takes a long time before an IC fails. Several methods have been proposed in the literature to reduce the time required for testing one type of IC. The author considers the problem of estimating the mean life of I types of IC (I>1). Assuming that the lifetime distribution of the ICs is exponential and at most N ICs can be tested concurrently, it is shown that the optimal life testing schedule that requires the smallest mean testing time is to test N ICs of type 1, then test N ICs of type 2,. . . and finally test N ICs of type I