Low-temperature hysteresis effects in metal-oxide-silicon capacitors caused by surface-state trapping

At low temperatures, charge exchange in all surface states except those close to the band edges can occur only by capture of free carriers because emission rates become very slow. If means are provided to supply minority carriers (either from an extended inversion layer or in a gate-controlled diode), pronounced charge-trapping effects can be observed. A ledge in the C-V characteristic is identified as being due to the charging of almost all surface states within the forbidden gap at a surface potential dependent on surface-state density, capture cross section and voltage sweep rate. Capture cross sections at low temperatures can be estimated from the onset of the ledge. When the C-V curves are traced from accumulation to inversion the capacitance drops below the equilibrium minimum value into depletion and increases rapidly when inversion is reached. This "hook" is caused by a barrier against minority carrier flow at the boundary of the MOS capacitor. The barrier disappears when sufficient voltage is applied to charge the surface states in the boundary region.