• DocumentCode
    1034656
  • Title

    Testing of complex gates

  • Author

    Rajsuman, R. ; Jayasumana, A.P. ; Malaiya, Y.K.

  • Author_Institution
    Colorado State University, Department of Electrical Engineering, Fort Collins, USA
  • Volume
    23
  • Issue
    16
  • fYear
    1987
  • Firstpage
    813
  • Lastpage
    814
  • Abstract
    A systematic scheme for testing NMOS complex gates is presented. A minimal complete test set for all single and multiple detectable s-open, s-on and bridging faults is obtained. The scheme can easily be extended to test any general NMOS complex gate.
  • Keywords
    field effect integrated circuits; integrated circuit testing; integrated logic circuits; logic testing; MOS devices; any general NMOS complex gate; bridging faults; minimal complete test set; multiple faults; s-on; s-open; stuck on faults; stuck open faults; systematic scheme; testing NMOS complex gates;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19870576
  • Filename
    4257913
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1034656