Title :
Fast parallel-prefix modulo 2n+1 adders
Author :
Efstathiou, Costas ; Vergos, Haridimos T. ; Nikolos, Dimitris
Author_Institution :
Informatics Dept., TEI of Athens, Greece
Abstract :
Modulo 2n+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units, the first architecture utilizes a fast carry increment stage, whereas the second is a totally parallel-prefix solution. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and execution latency.
Keywords :
adders; carry logic; logic gates; parallel architectures; residue number systems; CMOS implementations; RNS implementations; binary adders; cryptography; parallel-prefix carry computation units; parallel-prefix modulo 2n+1 adders; Adders; Arithmetic; Computer architecture; Concurrent computing; Cryptography; Delay; Digital filters; Discrete Fourier transforms; Discrete cosine transforms; Fourier transforms; 65; Index Terms- Binary adders; RNS.; modulo 2^n+1 arithmetic; parallel-prefix adders;
Journal_Title :
Computers, IEEE Transactions on
