DocumentCode :
1035262
Title :
New clustering approach to chip floorplan using functional data
Author :
Harada, I. ; Adachi, Toru
Author_Institution :
NTT, Integrated Circuit Applications Section, Electrical Communications Laboratories, Atsugi, Japan
Volume :
23
Issue :
17
fYear :
1987
Firstpage :
900
Lastpage :
902
Abstract :
An approach to chip floorplanning utilising hierarchical and functional information derived using LSI logic design is described. The proposed approach adopts a methodological design process similar to that of expert designers. A new clustering method that can be divided into three phases, namely clustering, cluster classification and placement, is employed in this process. The prototype system is implemented based on AI techniques.
Keywords :
circuit layout CAD; integrated circuit technology; large scale integration; logic CAD; AI techniques; CAD; LSI logic design; chip floorplan; classification; clustering approach; computer aided design; functional data; hierarchical information; methodological design process; placement;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19870636
Filename :
4257974
Link To Document :
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