Title :
The laminated overlay transistor, a status report
Author :
Amantea, R. ; Becke, H.W. ; White, J.P.
fDate :
2/1/1969 12:00:00 AM
Keywords :
Breakdown voltage; Electronic components; Epitaxial layers; Heat sinks; Impedance; Impurities; Laboratories; P-n junctions; Semiconductor process modeling; Transistors;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1969.16663
