Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges

Author

Wu, Wen-Chung S. ; Helms, Ward J. ; Kuhn, Jay A. ; Byrkett, Bruce E.

Author_Institution

Cirrus Logic Inc., Fremont, CA, USA

Volume

29

Issue

1

fYear

1994

fDate

1/1/1994 12:00:00 AM

Firstpage

63

Lastpage

66

Abstract

This paper presents a CMOS buffer amplifier which operates on a single 5-V power supply. The uniquely symmetrical design adds the following advantages: rail-to-rail linear, symmetrical operation at both the input and output; the output stage allows the use of gate channel capacitors of standard MOSFET´s as the compensation capacitor saving die area from 80%~93% in a standard single polysilicon digital process; large gain-bandwidth product; high power supply rejection ratio; good common-mode rejection ratio; and easy compact layout suitable for design automation (layout as a parametric cell, allows easy adaption to changing processes). The buffer is capable of driving 300 Ω||100 pF with a loaded gain-bandwidth product of more than 4 MHz and a fully loaded slew rate of greater than 4 V/μS

Keywords

CMOS integrated circuits; buffer circuits; linear integrated circuits; operational amplifiers; 100 pF; 300 ohm; 5 V; CMOS buffer amplifier; MOSFET; common-mode rejection ratio; compact layout; compensation capacitor; fully loaded slew rate; gain-bandwidth product; gate channel capacitors; high-performance operational amplifier; linear symmetrical operation; power supply rejection ratio; rail-to-rail input range; rail-to-rail output range; single polysilicon digital process; symmetrical design; Capacitors; Circuits; Design automation; MOS devices; Operational amplifiers; Power supplies; Rail to rail amplifiers; Rail to rail inputs; Threshold voltage; Transconductance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.272096

Filename

272096