Multifrequency zero-jitter delay-locked loop

Author

Efendovich, Avner ; Afek, Yachin ; Sella, Coby ; Bikowsky, Zeev

Author_Institution

Nat. Semicond. (I.C.) Ltd., Herzlya, Israel

Volume

29

Issue

1

fYear

1994

fDate

1/1/1994 12:00:00 AM

Firstpage

67

Lastpage

70

Abstract

The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times. Changes in the operating frequency are possible, without falling out of synchronization. Due to the special lead-lag phase detector, the jitter of the clock is zero, when the loop is locked, under any working conditions

Keywords

CMOS integrated circuits; clocks; digital integrated circuits; logic design; phase-locked loops; synchronisation; all-digital phase locked loop; bus utilization; frequency switching; lead-lag phase detector; master CPU; multifrequency zero-jitter delay-locked loop; multiple clock synthesis; processing units; slave system chip; synchronization; twin-well CMOS process; Central Processing Unit; Circuits; Clocks; Delay; Detectors; Frequency synchronization; Jitter; Master-slave; Phase detection; Phase locked loops;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.272097

Filename

272097