Self-aligned diffusion technique for n-InP JFETs

A self-aligned diffusion process has been demonstrated in the fabrication of n-InP JFETs on semi-insulating InP. This process utilises the anisotropic and selective etching properties of InP/GaInAs materials. Using this technique, sub-micrometre gate lengths can be achieved even with conventional photolithography. Devices with trans-conductance of >35mS/mm, leakage current of < 10nA/mm and gate capacitance of <0.7pF/mm have been fabricated with a cutoff frequency of 7 GHz.