Author_Institution :
Tatung Institute of Technology, Department of Electrical Engineering, Taipei, Republic of China
Abstract :
The letter describes a parallel merger for the sort-merger scheme in a hardware sorter. The technique offers k times the data throughput of conventional hardware k-way mergers.
Keywords :
buffer storage; parallel architectures; architecture design technique; comparators; data throughput enhancement; hardware k-way mergers; hardware sorter; interleaving buffers; parallel merger; parallel processing;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19870747
