• DocumentCode
    1037054
  • Title

    Almost sure diagnosis of almost every good element [logic testing]

  • Author

    La Forge, L.E. ; Huang, Kaiyuan ; Agarwal, Vinod K.

  • Author_Institution
    Dept. of Electr. Eng., Nevada Univ., Reno, NV, USA
  • Volume
    43
  • Issue
    3
  • fYear
    1994
  • fDate
    3/1/1994 12:00:00 AM
  • Firstpage
    295
  • Lastpage
    305
  • Abstract
    We demonstrate a structure for mutual test among N processing elements. We indicate how this structure might be used to identify the good dice on a semiconductor wafer at a cost below that of current techniques. Under either a digraph or a comparison model, our proposed test structure has the following properties: 1) It is nearly regular. 2) It can be laid out in area O(⊖(n). 3) In time ⊖(N) and with high probability, all but at most an arbitrarily small fraction of the good elements can be identified. 4) The number of tests or comparisons per element is bounded by a constant. We approximate this constant analytically. The result is a substantial savings over the ⊖(log N) tests per element in regular structures whose purpose is to identify, with high probability, every good element. In contrast with the majority of previous work, our results apply even when less than half of the elements are good
  • Keywords
    circuit reliability; directed graphs; logic testing; almost every good element; almost sure diagnosis; comparison model; digraph; mutual test; processing elements; semiconductor wafer; Circuit faults; Circuit testing; Conferences; Costs; Logic testing; Performance evaluation; Semiconductor device modeling; Semiconductor device testing; System testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.272430
  • Filename
    272430