Title :
Novel CMOS latch with clock hysteresis
Author_Institution :
Racal Research Limited, Reading, UK
Abstract :
A latch circuit is described which tolerates the use of slow and skewed clock signals. The low-complexity circuit has been shown to provide a safe alternative to the use of non-overlapping clocks, and enables the minimisation of clock interconnection and power.
Keywords :
CMOS integrated circuits; VLSI; clocks; digital integrated circuits; flip-flops; CMOS latch; clock hysteresis; clock interconnection; clock power; latch circuit; nonoverlapping clocks; skewed clock signals; slow clock signals;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19870850
