Flexible high-speed Fastbus master for data read-out and preprocessing

A single-slot Fastbus master module is described. It can be used for readout and preprocessing of data that are read out from Fastbus modules, e.g. an ADC (analog-to-digital converter) system. The module consists of a 25-MHz, 32-b processor MC68030 with cache memory and memory management, a floating-point coprocessor MC68882, 4 MB of main memory, and Fastbus master and slave interfaces. The main memory is multiported and can be accessed directly by the CPU, the Fastbus, and external masters via the high-speed local bus, which is accessible by way of a connector. The Fastbus interface supports most of the standard operations in master and slave mode. An asynchronous state machine converts the microprocessor transfer protocol to Fastbus operations and thus the MC68030 operates as a native processor on the Fastbus. Due to the architecture chosen, each Access of the processor to the Fastbus space causes the execution of a complete Fastbus transfer sequence, e.g. a primary address cycle, a secondary address cycle, and a data cycle. This simplifies the programming of the Fastbus master considerably