• DocumentCode
    1037990
  • Title

    Evolution of the PowerPC architecture

  • Author

    Diefendorff, Keith ; Oehler, Rich ; Hochsprung, Ron

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • Volume
    14
  • Issue
    2
  • fYear
    1994
  • fDate
    4/1/1994 12:00:00 AM
  • Firstpage
    34
  • Lastpage
    49
  • Abstract
    The PowerPC is a new RISC architecture derived from IBM´s POWER architecture. The changes made to POWER simplify implementations, increase clock rates, enable a higher degree of superscalar execution, extend the architecture to 64 bits, and add multiprocessor support. For compatibility with existing software, the developers retained POWER´s basic instruction set, opcode assignments, and programming model.<>
  • Keywords
    computer architecture; reduced instruction set computing; IBM´s POWER architecture; PowerPC architecture; RISC architecture; multiprocessor support; opcode assignments; programming model; Clocks; Computer aided instruction; Computer architecture; Delay; High performance computing; Pipelines; Power generation; Power system modeling; Reduced instruction set computing; Software performance;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.272836
  • Filename
    272836
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1037990