Fabrication of integrated circuits using the electron image projection system (ELIPS)

ELIPS is based on the use of an electron image tube principle to project large area (5-cm diameter) ultrahigh resolution (1 micron) electron images from a patterned photocathode onto an electron-sensitive resist layer, thereby replacing the conventional photoresist optical procedures in integrated circuit fabrication [1]. Integrated circuits of minimum linewidths of 0.5 mil have been fabricated to show the practicality of the technique through the full set of mask exposures necessary for a DZTL quad dual input NAND gate. The necessary alignments between successive masks were achieved by an optical dead reckoning technique which allowed the electron image to be adjusted in position and orientation from a known "zero" position to the separately determined location of the pre-existing pattern on the sample. Accuracy of such alignments was ± 2 micron. The much more desirable alignment technique, in which simple devices in the form of alignment marks on the target wafer detect separate electron beams emanating from the cathode, allows rapid alignment to submicron registration and the potential for the complete automation of alignment and exposure. The system provides for the rapid registration and exposure of wafers at high resolution over large areas with great depth of focus under vacuum clean, contactless conditions using an electroresist insensitive to ambient light. It makes practical the fabrication of very high-density planar devices allowing extremely complex large area circuits to be formed. Patterned photocathodes were fabricated by conventional photoresist techniques for the DZTL circuit discussed. For high-resolution (1 micron) patterns, cathodes can be defined in the electron micro-plotter (computer-controlled scanning electron microscope).