The single-chip Fastbus slave interface

A single-chip implementation of the general-purpose Fastbus slave interface (FSI) has been developed in ECL (emitter-coupled logic) gate-array technology. The FSI occupies only 1.6% of the available circuit board space while providing a complete 32-b interface to the Fastbus. For slaves with 15-ns response timing, the maximum data rate expected with the single-chip interface is 25 MHz for all types of data cycles. All mandatory slave-interface requirements of IEEE 960 are supported, in addition to several nonmandatory requirements and the optional, extended MS code features. Geographic, logical, and broadcast addressing are implemented using on-chip registers. An optional multiple-module addressing technique is included that allows participating modules residing on a common crate or cable segment to respond as if individually addressed in sequence. The user interface provided by the FSI allows control of slave status-response and connection timing for both address and data cycles. The BIT1 ECL array technology used for the FSI allows direct connections to the Fastbus, eliminating the need for external driver/receiver buffers