Title :
Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test
Author :
Chen, Chien-In Henry ; George, Kiran
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.
Keywords :
automatic test pattern generation; built-in self test; electronic engineering computing; fault location; feedback; shift registers; system-on-chip; automated synthesis procedure; chip-level BIST; hardware overhead; line feedback shifter; parallel built-in self-test; random patterns; random-pattern-detectable faults; random-pattern-resistant faults; serial built-in self-test; system-on-a-chip BIST; test generator; test patterns; test-per-clock; test-per-scan; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Feedback; System-on-a-chip; Test pattern generators; Two dimensional displays; BIST; Built-in self-test; SoC; linear feedback shifter registers; parallel BIST; scan path; serial BIST; sytem-on-a-chip;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
DOI :
10.1109/TIM.2004.830790
