Estimating fatigue lifetime of power-cycled solid-state switches

A description is given of a method for estimating the fatigue lifetime of a solid-state power switch. The switch considered is a layered structure with a silicon wafer as a power-dissipating structure from which heat flows through a solder layer into a copper heat sink. Lifetime data and metallographic analyses are presented for devices operating at 80-, 60-, and 40-amperes rms with fatigue lifetimes in excess of 10⁶cycles. The data are in substantial agreement with the theory.