Title :
Testing Logic Networks and Designing for Testability
Author :
Williams, Thomas W. ; Parker, Kenneth P.
Abstract :
VLSI has brought exciting increases in circuit density and performance capability. But it has also aggravated the problem of chip, component and system testing. Here are some approaches to dealing with that problem.
Keywords :
Automatic test pattern generation; Automatic testing; Large scale integration; Logic design; Logic gates; Logic testing; Test pattern generators; Very large scale integration;
DOI :
10.1109/MC.1979.1658490
