DocumentCode
1040663
Title
A built-in parametric timing measurement unit
Author
Hsiao, Ming-Jun ; Huang, Jing-Reng ; Chang, Tsin-Yuan
Author_Institution
Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
21
Issue
4
fYear
2004
Firstpage
322
Lastpage
330
Abstract
On-chip timing-measurement units are needed because accessibility to internal nodes in SoCs is very limited, and performing time interval measurements using automatic test equipment is very difficult and expensive. We present a parametric timing measurement solution, which uses self-timed techniques and delivers high linearity and improved accuracy, at low risk of measurement error. Performing the time-to-digital conversion via built-in circuitry allows accurate measurement of short time intervals and setup/hold time. This circuitry coordinates well with low-cost ATE. To achieve this solution, researchers have used techniques such as delay matrices, phase-locked loops (PLLs), and dual-slope conversion.
Keywords
automatic test equipment; built-in self test; phase locked loops; system-on-chip; timing circuits; SoC; automatic test equipment; built-in circuitry; delay matrices; dual-slope conversion; on-chip timing-measurement unit; phase-locked loop; self-timed techniques; time interval measurement; time-to-digital conversion; Automatic test equipment; Circuits; Delay; Linearity; Measurement errors; Measurement units; Performance evaluation; Phase locked loops; Time measurement; Timing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2004.22
Filename
1316779
Link To Document