Very fast carry energy efficient computation based on mixed dynamic=transmission-gate full adders

A circuit approach based on the adoption of mixed dynamic and transmission-gate full adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and allows the design to exceed the speed performance of fast Domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90%nm CMOS technology are presented to validate the results.