The latchup risk of CMOS-technology in space

Author

Moreau, Yves ; De la Rochette, Hélène ; Bruguier, Guy ; Gasiot, Jean ; Pélanchon, Frédéric ; Sudre, Christophe ; Ecoffet, Robert

Author_Institution

Centre d´´Electron. de Montpellier, France

Volume

40

Issue

6

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1831

Lastpage

1837

Abstract

The use of CMOS technology in space requires the careful evaluation of the latchup risk. The radiation tolerance of a standard 1.0 μm high density technology and its hardened variants is studied. The internal currents and densities are read through dynamic two/three dimensional device simulations, performed on a complete description of the CMOS inverter cell and a simulated heavy ion strike. An evaluation of the capture cross section versus the ion energy is derived from the statistical distribution of ion tracks through the structure

Keywords

CMOS integrated circuits; circuit analysis computing; integrated circuit technology; ion beam effects; radiation hardening (electronics); semiconductor device models; 1 micron; CMOS inverter cell; CMOS technology; capture cross section; dynamic 2D simulation; dynamic 3D simulation; high density technology; internal currents; ion track statistical distribution; latchup risk; radiation hardening; radiation tolerance; simulated heavy ion strike; space; CMOS process; CMOS technology; Computational modeling; Doping profiles; Epitaxial layers; Inverters; MOS devices; Medical simulation; Space technology; Substrates;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.273473

Filename

273473