Design considerations for a radiation hardened nonvolatile memory

Author

Murray, James R.

Author_Institution

Sandia Nat. Lab., Albuquerque, NM, USA

Volume

40

Issue

6

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1610

Lastpage

1618

Abstract

The authors discuss the design techniques used in the development of a 64 K EEPROM (electrically erasable programmable read-only memory) to maximize radiation hardness. Radiation testing has been performed on the 64 K EEPROM, demonstrating total dose hardness of greater than 1 Mrad (Si), immunity to data loss in a transient environment of greater than 1.4×10¹¹ rad(Si)/s, a write upset level of greater than 3×10⁹ rad(Si)/s, and a read upset level of greater than 1×10⁸ rad(Si)/s. The SEU (single event upset) soft error level ranged from an LET (linear energy transfer) of 35 to 50 MeV-cm²/mg for the various latches. Design modifications for reducing the standby current in a weapon environment and for increasing the transient upset level in the read mode are presented. The value of circuit simulations for predicting the radiation response of a nonvolatile memory and as well as for diagnosing radiation failures has been demonstrated

Keywords

CMOS integrated circuits; EPROM; aerospace instrumentation; gamma-ray effects; military equipment; radiation hardening (electronics); 64 Kbit; CMOS/SNOS technology; EEPROM; LET; SEU; circuit simulations; design techniques; radiation hardened nonvolatile memory; radiation response; read upset level; soft error level; standby current; total dose hardness; transient upset level; weapon environment; write upset level; Circuit simulation; EPROM; Energy exchange; Latches; Nonvolatile memory; PROM; Performance evaluation; Radiation hardening; Single event upset; Weapons;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.273499

Filename

273499