Partial-switching two-core-per-bit memory design considerations

The partial-switching two-core-per-bit mode of operation offers significant speed advantages for ferrite core memories. A number of problems must be solved in designing such a memory; some of these problems are directly related to the use of ferrite cores in the partial-switching mode, others are more or less common to many kinds of high-speed memories. The first kind of problems includes the behavior of the core pair as a function of thermal and information history and the design parameters for the core. The second kind concerns the economic optimization constrained by the technological possibilities. Both kinds of design problems are treated in this paper and it is concluded that memories of 0.1 to 1 million bits using the partial-switching two-core-per-bit mode with cycle times of 200-300 ns are economically and technologically feasible.