• DocumentCode
    1041937
  • Title

    On internal-external layouts

  • Author

    Tollis, Ioannis G.

  • Author_Institution
    Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
  • Volume
    36
  • Issue
    1
  • fYear
    1989
  • fDate
    1/1/1989 12:00:00 AM
  • Firstpage
    154
  • Lastpage
    156
  • Abstract
    E.L. Lloyd and S.S. Ravi recently (1984) considered the problem of writing in a channel using one layer. They restricted their investigation to the river-routing problem and defined two classes of layouts, fully internal and internal-external layouts. The approach of internal-external layout is more powerful and it can solve problems more generally than the river-routing problem. Determining the conditions under which an arbitrary channel routing problem admits an internal-external layout is mentioned as an interesting open problem. A complete characterization of channel routing problems that admit an internal-external layout is presented, and a linear-time algorithm for testing if a channel routing problem admits such a layout is proposed
  • Keywords
    VLSI; circuit layout; graph theory; network topology; VLSI; channel routing; internal-external layouts; linear-time algorithm; testing; Circuits and systems; Delay lines; Digital filters; Equations; Filtering; Neural networks; Rivers; Routing; TV; Timing;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/31.16587
  • Filename
    16587