• DocumentCode
    1042730
  • Title

    Device Design and Optimization Considerations for Bulk FinFETs

  • Author

    Manoj, C.R. ; Nagpal, Meenakshi ; Varghese, Dhanya ; Rao, V. Ramgopal

  • Author_Institution
    Indian Inst. of Technol.-Bombay, Mumbai
  • Volume
    55
  • Issue
    2
  • fYear
    2008
  • Firstpage
    609
  • Lastpage
    615
  • Abstract
    Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.
  • Keywords
    CMOS integrated circuits; MOSFET; semiconductor device models; 3-D mixed mode simulations; bulk CMOS fabrication; device models; device parasitics; nanoscale bulk FinFET; CMOS process; CMOS technology; Costs; Design methodology; Design optimization; Doping; Fabrication; FinFETs; Semiconductor device modeling; Silicon on insulator technology; Bulk FinFET; SOI FinFET; device parasitics; fringe capacitance; inverter delay;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2007.912996
  • Filename
    4436001