Resistive signal line wiring net designs in multichip modules

To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, formulas with one pole and one zero on the negative real axis are proposed. The algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source, are derived. The far end of this line is either open-circuited or terminated by a constant resistance load. Nomographs to guide the multichip module (MCM) wiring net designs are developed and presented. Their application is illustrated by an MCM-D address bus wiring net design example