• DocumentCode
    1043378
  • Title

    Combining ESOP minimization with BDD-based decomposition for improved FPGA synthesis

  • Author

    Muma, K. ; Dongdong Chen ; Younhee Choi ; Dodds, D. ; Moon Ho Lee ; Seok-Bum Ko

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Saskatchewan, Saskatoon, SK
  • Volume
    33
  • Issue
    42433
  • fYear
    2008
  • Firstpage
    177
  • Lastpage
    182
  • Abstract
    This paper proposes a novel method to improve the utilization efficiency and performance of field-programmable gate arrays (FPGAs). The proposed method, ExorBDD, uses a stage of exclusive-sum-of-product (ESOP) minimization, followed by a stage of decomposition using binary decision diagrams (BDDs). For exclusive OR (XOR)-intensive circuits, experiments were conducted on 19 MCNC benchmark parity circuits (ranging from 5 to 25 inputs), as they are the most representative case of XOR-intensive circuits. The results using the proposed approach show significant improvements over Exorcism4, BDS, and commercial tools. On average, the new approach uses only 30.3% as many look-up tables as are used by Xilinx tools (and only 16.4% in comparison to Altera). On average, the new approach has a maximum combinational path delay of 89.2% compared to the delay with Xilinx tools (80.3% compared to Altera). Experiments were also conducted on non-XOR-intensive circuits. These results show that ExorBDD also performs well for arbitrary circuits.
  • Keywords
    binary decision diagrams; field programmable gate arrays; logic circuits; logic design; BDD-based decomposition; ESOP minimization; FPGA synthesis; benchmark parity circuits; binary decision diagrams; exclusive OR intensive circuits; exclusive-sum-of-product minimization; field-programmable gate arrays; maximum combinational path delay; utilization efficiency; Binary decision diagrams; Boolean functions; Circuits; Costs; Data structures; Delay; Field programmable gate arrays; Minimization methods; Moon; Programmable logic arrays; BDD decomposition; CAD; ESOP minimization; FPGA;
  • fLanguage
    English
  • Journal_Title
    Electrical and Computer Engineering, Canadian Journal of
  • Publisher
    ieee
  • ISSN
    0840-8688
  • Type

    jour

  • DOI
    10.1109/CJECE.2008.4721635
  • Filename
    4721635