Circuit analysis and optimization driven by worst-case distances

Author

Antreich, Kurt J. ; Graeb, Helmut E. ; Wieser, Claudia U.

Author_Institution

Inst. of Electron. Des. Autom., Tech. Univ. Munchen, Germany

Volume

13

Issue

1

fYear

1994

fDate

1/1/1994 12:00:00 AM

Firstpage

57

Lastpage

71

Abstract

In this paper, a new methodology for integrated circuit design considering the inevitable manufacturing and operating tolerances is presented. It is based on a new concept for specification analysis that provides exact worst-case transistor model parameters and exact worst-case operating conditions. Corresponding worst-case distances provide a key measure for the performance, the yield, and the robustness of a circuit. A new deterministic method for parametric circuit design that is based on worst-case distances is presented. It comprises nominal design, worst-case analysis, yield optimization, and design centering. In contrast to current approaches, it uses standard circuit simulators and at the same time considers deterministic design parameters of integrated circuits at reasonable computational costs. The most serious disadvantage of geometric approaches to design centering is eliminated, as the method´s complexity increases only linearly with the number of design variables

Keywords

CMOS integrated circuits; buffer circuits; circuit analysis computing; computational complexity; integrated logic circuits; switched capacitor filters; CMOS buffer amplifier; CMOS inverter; circuit analysis; circuit robustness; circuit simulators; computational complexity; design centering; deterministic method; integrated circuit design methodology; parametric circuit design; specification analysis; switched capacitor filter; tolerance bodies; worst-case distances; worst-case operating conditions; worst-case transistor model parameters; yield optimization; Circuit analysis; Circuit synthesis; Computational modeling; Design optimization; Integrated circuit manufacture; Integrated circuit measurements; Integrated circuit synthesis; Integrated circuit yield; Pulp manufacturing; Robustness;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.273749

Filename

273749