DocumentCode :
1043497
Title :
A Spur Elimination Technique for Phase Interpolation-Based Fractional- 
PLLs
Author :
Pamarti, Sudhakar ; Delshadpour, Siamak
Author_Institution :
Electr. Eng. Dept., California Univ., Los Angeles, CA
Volume :
55
Issue :
6
fYear :
2008
fDate :
7/1/2008 12:00:00 AM
Firstpage :
1639
Lastpage :
1647
Abstract :
A fractional spur elimination technique that enables wide-bandwidth phase interpolation-based fractional-N phase-locked loops (PLLs) is proposed. The technique uses specially filtered dither to eliminate the spurious tones otherwise caused by inevitable phase errors. The design of a wide-bandwidth fractional-N PLL based on the spur elimination technique and a theoretical proof of the proposed technique are presented.
Keywords :
error statistics; filtering theory; interpolation; phase locked loops; phase interpolation-based fractional-N PLL; phase-locked loops; spur elimination technique; wide-bandwidth phase interpolation; Delta-sigma modulation; Fractional-N phase locked loop; delta sigma modulation; error statistics; fractional-$N$
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2008.916571
Filename :
4436076
Link To Document :
