Title :
A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet
Author :
Yang, Rong-Jyi ; Chen, Shang-Ping ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 3.125-Gb/s clock and data recovery (CDR) circuit using a half-rate digital quadricorrelator frequency detector and a shifted-averaging voltage-controlled oscillator is presented for 10-Gbase-LX4 Ethernet. It can achieve low-jitter operation and improve pull-in range without a reference clock. This CDR circuit has been fabricated in a standard 0.18-μm CMOS technology. It occupies an active area of 0.6 × 0.8 mm2 and consumes 83 mW from a single 1.8-V supply. The measured bit-error rate is less than 10-12 for 27 - 1 PRBS 3.125-Gb/s data. It can meet the jitter tolerance specifications for the 10-Gbase-LX4 Ethernet application.
Keywords :
CMOS digital integrated circuits; clocks; error statistics; jitter; local area networks; synchronisation; timing circuits; 0.18 micron; 1.8 V; 10-Gbase-LX4 Ethernet; 3.125 Gbit/s; 83 mW; CMOS technology; bit-error rate; clock recovery circuit; data recovery circuit; half-rate digital quadricorrelator frequency detector; jitter tolerance specifications; low-jitter operation; pull-in range; reference clock; shifted-averaging voltage-controlled oscillator; CMOS technology; Circuits; Clocks; Detectors; Ethernet networks; Frequency; Jitter; Optical fiber communication; Optical receivers; Voltage-controlled oscillators; CDR; Clock and data recovery; frequency detector; quadricorrelator;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.831809
