DocumentCode :
1043614
Title :
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
Author :
Nosaka, Hideyuki ; Sano, Eiichi ; Ishii, Kiyoshi ; Ida, Minoru ; Kurishima, Kenji ; Yamahata, Shoji ; Shibata, Tsugumichi ; Fukuyama, Hiroyuki ; Yoneyama, Mikio ; Enoki, Takatomo ; Muraguchi, Masahiro
Author_Institution :
NTT Photonics Labs., NTT Corp., Atsugi, Japan
Volume :
39
Issue :
8
fYear :
2004
Firstpage :
1361
Lastpage :
1365
Abstract :
We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 231 - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.
Keywords :
III-V semiconductors; bipolar logic circuits; clocks; digital phase locked loops; gallium arsenide; indium compounds; integrated circuit design; phase locked loops; synchronisation; timing circuits; timing jitter; voltage-controlled oscillators; 39 to 45 Gbit/s; CDR IC; CDR circuit; Darlington-type voltage-controlled oscillator; FSPC circuit; InP-InGaAs; exclusive-NOR gate; frequency acquisition; frequency search; heterojunction bipolar transistor circuit; multidata-rate clock data recovery circuit; peak-to-peak jitter; phase control; phase-locked loop; rms jitter; robust lock detector; Circuits; Clocks; Detectors; Error-free operation; Frequency; Indium gallium arsenide; Indium phosphide; Phase control; Robustness; Voltage-controlled oscillators; 40G; CDR; Clock and data recovery; HBT; InP; PLL; VCO; jitter; phase-locked loop; voltage-controlled oscillator;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2004.831463
Filename :
1317064
Link To Document :
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