Title :
A low-jitter mutual-correlated pulsewidth control loop circuit
Author :
Lin, Wei-Ming ; Huang, Hong-Yi
Author_Institution :
Dept. of Electron. Eng., Fu-Jen Catholic Univ., Hsin-Chuang, Taiwan
Abstract :
This work presents a low-jitter pulsewidth control loop (PWCL) circuit. A mutual-correlated scheme is implemented to adjust the duty cycle and increase the stability of the PWCL. The design is less sensitive to process variation. The jitter induced by voltage ripple is suppressed. The circuit is implemented using 0.35 μm 1P4M CMOS process. The area of the PWCL is 136 × 143 μm2. At an operating frequency of 300 MHz, the power dissipation and voltage ripple are reduced by 35.4% and 93.7%, respectively. A test chip is successfully verified to obtain 42-ps jitter at an operating frequency of 900 MHz.
Keywords :
CMOS integrated circuits; jitter; phase locked loops; 0.35 micron; 1P4M CMOS; 300 MHz; 42 ps; 900 MHz; CMOS integrated circuits; PWCL circuit; clocks; duty cycle; jitter; low-jitter pulsewidth control loop; mutual-correlated scheme; phase-locked loops; power dissipation; test chip verification; voltage ripple; Charge pumps; Delay; Frequency; Jitter; Phase locked loops; Pulse circuits; Ring oscillators; Space vector pulse width modulation; Transconductors; Voltage; CMOS integrated circuits; Clocks; duty cycle; jitter; phase-locked loops; pulsewidth control loop circuit;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.831499
