Title :
Design on ESD protection scheme for IC with power-down-mode operation
Author :
Ker, Ming-Dou ; Lin, Kun-Hsien
Author_Institution :
Nanoelectronics & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-μm silicided CMOS process.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit testing; leakage currents; protection; 0.35 micron; 7.5 kV; ESD clamp circuits; ESD protection design; ESD protection scheme; HBM ESD level; I/O pin; IC protection; VDD ESD bus line; VDD ESD diodes; VDD power line; VSS power line; electrostatic discharge; human-body model; leakage current; power-down mode; power-down-mode operation; silicided CMOS process; CMOS process; Circuits; Clamps; Diodes; Electrostatic discharge; Leakage current; Power system protection; Stress; Variable structure systems; Voltage; ESD; ESD bus; ESD protection scheme; Electrostatic discharge; leakage current; power-down mode;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.831501
