Design optimization of AlInAs-GalnAs HEMTs for low-noise applications

In order to optimize the low-noise performance of 50-nm-gate AlInAs-GalnAs high-electron mobility transistors (HEMTs), by using an ensemble Monte Carlo simulation we study the influence of three important technological parameters on their noise level: the doping of the δ-doped layer, the width of the devices and the length of the recess. The noise behavior of the devices is firstly analyzed in terms of the physics-based P, R, and C parameters, and then characterized from a practical (circuit oriented) point of view through their four noise parameters: minimum noise figure, F_min, noise resistance, R_n, and complex input admittance, Y_opt (or reflection coefficient, Γ_opt). We have observed an enhancement of the noise when the δ-doping or the device width are increased (a deterioration parallel to that of f_max). Thus, the optimum noise operation is obtained for the lowest possible values of the δ-doping and device width. However, for small width the effect of the offset parasitic capacitances makes F_min increase, thus, imposing a limit for the reduction of the noise. Moreover, the increase of R_n for small W makes the noise tuning condition critical to reach the optimum low-noise operation. We have also confirmed that when shortening the recess length from 100 to 20 nm at each side of the gate F_min is reduced, with a slight deterioration of f_max, while the static characteristics are not modified.