DocumentCode :
1044579
Title :
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications
Author :
Molina, María C. ; Ruiz-Sautua, Rafael ; García-Repetto, Pedro ; Hermida, Román
Author_Institution :
Dept. of Comput. Archit. & Syst. Eng., Complutense Univ. of Madrid, Madrid
Volume :
28
Issue :
1
fYear :
2009
Firstpage :
60
Lastpage :
73
Abstract :
Conventional high-level synthesis algorithms treat specification operations as atomic elements that are executed in one or several consecutive cycles and over one functional unit. However, in most specifications, there exist different types, representations, and widths of operations that, handled at different decomposition levels, may produce better designs. In this way, most arithmetic operations can be decomposed into smaller operations, applying several arithmetical properties. Different decompositions can be performed in order to improve the performance or reduce the area or power consumption. In this paper, we propose a pattern-based design methodology that is able to treat every operation at its most appropriate decomposition level. It produces reduced datapaths while meeting specified time constraints. In comparison to conventional algorithms, the amount of area saved averages 40%.
Keywords :
high level synthesis; multiplying circuits; arithmetical operations; atomic elements; behavioral specification; frequent-pattern-guided multilevel decomposition; high-level synthesis algorithm; pattern-based design methodology; time-constrained HLS algorithm; Arithmetic; Circuits; Clocks; Design methodology; Energy consumption; Hardware; Helium; High level synthesis; Pattern matching; Time factors; Allocation; binding; high-level synthesis (HLS); pattern matching; scheduling;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2008.2009140
Filename :
4723642
Link To Document :
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