A terminal multiplexor application of Ovonic memories

A special purpose computer intended primarily for use as a terminal multiplexor has been constructed. Program storage for the processor is implemented using an Ovonic read-mostly memory. In addition a bipolar scratchpad memory is implemented for data buffering and status information storage. The processor organization and the Ovonic memory design are discussed. The Ovonic memory is modular in 2048-bit increments to 8192 bits. It has an access time of 70 ns and a cycle time of 125 ns. The processor executes three million instructions per second and can support up to 128 mixed terminal devices with minimum interface circuitry. The ability to alter the program store provides needed flexibility to reconfigure the complement of terminal devices.