Title :
Low-latency bit-parallel systolic multiplier
Author :
Pekmestzi, K.Z. ; Caraiscos, C.
Author_Institution :
Dept. of Electr. Eng., Nat. Tech. Univ., Athens, Greece
Abstract :
A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.
Keywords :
digital arithmetic; multiplying circuits; systolic arrays; bit-parallel systolic multiplier; cellular array; gated full adder; latch; low latency design; pair-wise grouping;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19930247
