• DocumentCode
    1044753
  • Title

    Low-latency bit-parallel systolic multiplier

  • Author

    Pekmestzi, K.Z. ; Caraiscos, C.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tech. Univ., Athens, Greece
  • Volume
    29
  • Issue
    4
  • fYear
    1993
  • Firstpage
    367
  • Lastpage
    369
  • Abstract
    A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.
  • Keywords
    digital arithmetic; multiplying circuits; systolic arrays; bit-parallel systolic multiplier; cellular array; gated full adder; latch; low latency design; pair-wise grouping;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19930247
  • Filename
    274778
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1044753