Differential pixel-based low-power and high-speed implementation of DCT for on-board satellite image processing

Low-power and high-speed discrete cosine transform (DCT) implementation of the images captured by the satellites presents a hardware design problem. The cost of the DCT implementation is dominated by the complexity of the multiplication of input data (image) with the DCT matrix. The techniques for minimising the complexity of multiplication by employing a differential pixel method are presented. In the proposed method 8times8 blocks of input image matrix are considered, the difference between the adjacent pixels is calculated and those differential pixels are used in DCT transformation. Synthesis results on 0.18 mum CMOS technology show that the proposed method gives an average of 13.2% reduction in power consumption and 10.9% improvement in speed over the conventional method. The proposed method can also be combined with the common subexpression elimination method for further reduction.