Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Single event charge collection mechanisms in 90 nm triple-well NMOS devices are explained and compared with those of dual-well devices. The primary factors affecting the single event pulse width in triple-well NMOSFETs are the separation of deposited charge due to the n-well, potential rise in the p-well followed by the injection of electrons into the p-well by the source, and removal of holes by the p-well contact. Design parameters of p-wells, such as contact area, doping depth and placement, are varied to reduce single event pulse widths. Pulse width decreases as the area of the p-well contacts increases, the p-well contacts become deeper, and the p-well contacts are placed more frequently. Increasing the p-well-n-well junction depth also causes the full width half rail (FWHR) pulse width to decrease.