• DocumentCode
    1046591
  • Title

    Three-mask self-aligned MOS technology

  • Author

    Mai, C.C. ; Chan, T.C. ; Palmer, R.B.

  • Author_Institution
    Mostek Corporation, Worcester, Mass.
  • Volume
    20
  • Issue
    12
  • fYear
    1973
  • fDate
    12/1/1973 12:00:00 AM
  • Firstpage
    1162
  • Lastpage
    1164
  • Abstract
    A three-mask process has been developed which permits one to fabricate MOSFET or integrated circuits with self-aligned gate, reduce capacitance, and flatter surface topology. Ion implantation and silicon nitride layers were employed in this process.
  • Keywords
    Cathodes; Coupling circuits; Electrons; Integrated circuit technology; MOSFET circuits; Noise figure; Optical coupling; Silicon; Surface topography; Temperature;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1973.17813
  • Filename
    1477470
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1046591