DRO plated-wire development

Development of DRO plated-wire memory elements and tests in a 60-ns cycle-time memory of 26 000-bit capacity are reported. The experimental memory was fully populated with wire, but partially populated with electronics. Noise conditions of a full memory were simulated. The destructive readout (DRO) cycle utilized a single digit pulse as opposed to the bipolar digit pulses normally used in nondestructive readout (NDRO) wire memories. High-speed DRO plated wire has been prepared in a continuous process. Two thin Permalloy layers separated by copper are electrodeposited on a specially prepared wire substrate. The laminate approach combines the high disturb resistance and fast write switching of thinner films with the signal magnitude of thicker ones. In sacrificing the NDRO feature, improved tolerance to strain and aging were also noted.