Nano Magnetic STT-Logic Partitioning for Optimum Performance

Magnetoresistive RAMs (MRAMs) are the new generation of nonvolatile memories that use magnetic tunnel junctions (MTJs) to store bit information. Horizontal (bit and source) and vertical (word) lines partition the MRAM into a 2-D grid similar to a conventional memory. This paper relies on a logic-in-memory architecture where MRAM cells are placed in close proximity so that they can behave both as logic elements and as memory bits. When the clock signal is active the cells compute logic, while at other times the cells store the data in them and behave as memory. Using these MRAM cells, in this paper, we have designed two fundamental components in datapath and logic circuits, the XOR and majority. By transferring logic responsibilities between the metal lines, CMOS peripherals and the MTJs, we have achieved a significant reduction in MTJ cell count, energy, and delay over previous designs. For example, an energy savings of more than 75% and a cell reduction of more than 81.25% are obtained for a 2-input XOR in standalone mode of operation. Though this hybrid sharing of responsibilities between the MTJs and CMOS has apparently increased the overhead on CMOS, it has however reduced the net power consumption in the CMOS peripherals. This happens because the CMOS now has a fewer number of cells to control. The reduction in the CMOS power varies from close to 50% for a 2-input XOR to greater than 10% for a majority. In addition, the designs also obey the rules of hierarchical modeling which helped us to use the novel 2-input XORs as bricks for designing the novel 3-input XOR. Again a 3-input XOR and majority are used to custom develop a one-bit full adder. Together with an inter-cell spacing of 20 nm and low power spin transfer torque current-driven write and clock operations, the novel designs presented in this paper has the potential to target the low energy and high density logic-in-memory applications.