Graphical design and iterative analysis of the DC parameters of GaAs FET´s

Two-dimensional numerical solutions of Poisson´s equation and the carrier continuity equation for the short-gate GaAS field-effect transistor structure have been used to predict device performance. However, a generally accepted simplified approach to FET design has not evolved. In this paper, a simplified design technique and an iterative device analysis procedure are presented for application to GaAs FET´s with gate lengths as small as 1 µm. The design technique makes it possible to determine drain saturation current and saturation transconductance for any gate size by simply scaling the appropriate curves for an FET with a 1-µm gate. Curves are also presented that relate the effective transconductance to the intrinsic transconductance for any FET geometry. The iterative analysis procedure makes it possible to determine the doping, ND, and thickness, a, of the epitaxial layer on which the device is fabricated. By simply measuring drain current and transconductance at zero gate bias and the pinchoff voltage, a method is presented which allows the epi parameters to be determined in a self-consistent fashion. This technique provides a way of mapping NDand a over a slice, as opposed to the usual technique of simply measuring pinchoff voltage (only gives ND.a²product variations).